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CDP1851, CDP1851C
March 1997
CMOS Programmable I/O Interface
Description
THE CDP1851 and CDP1851C are CMOS programmable twoport I/Os designed for use as general-purpose I/O devices. They are directly compatible with CDP1800-series microprocessors functioning at maximum clock frequency. Each port can be programmed in either byte-I/O or bit-programmable modes for interfacing with peripheral devices such as printers and keyboards. Both ports A and B can be separately programmed to be 8-bit input or output ports with handshaking control lines, RDY and STROBE. Only port A can be programmed to be a bidirectional port. This configuration provides a means for communicating with a peripheral device or microprocessor system on a single 8-bit bus for both transmitting and receiving data. Handshaking signals are provided to maintain proper bus access control. Port A handshaking lines are used for input control and port B handshaking lines are used for output; therefore port B must be in the bit-programmable mode where handshaking is not used. Ports A and B can be separately bit programmed so that each individual line can be designated as an input or output line. The handshaking lines may also be individually programmed as input or output when port A is not in bidirectional mode. The CDP1851 has a supply-voltage range of 4V to 10.5V, and the CDP1851C has a range of 4V to 6.5V. Both types are supplied in 40-lead dual-in-line plastic (E suffix) or hermetic ceramic (D suffix) packages. The CDP1851C is also available in chip form (H suffix).
Features
* 20 Programmable I/O Lines * Programmable for Operation in Four Modes: - Input - Output - Bidirectional - Bit-programmable * Operates in Either I/O or Memory Space
Ordering Information
PACKAGE TEMP. RANGE PDIP Burn-In SBDIP Burn-In 5V 10V PKG. NO.
-40oC to +85oC CDP1851CE CDP1851CEX -40oC to +85oC CDP1851CD
CDP1851E E40.6 E40.6 D40.6
CDP1851CDX CDP1851DX D40.6
Pinout
CDP1851, CDP1851C (PDIP, SBDIP) TOP VIEW
CLOCK 1 CS 2 RA0 3 RA1 4 BUS0 5 BUS1 6 BUS2 7 BUS3 8 BUS4 9 BUS5 10 BUS6 11 BUS7 12 CLEAR 13 A INT 14 B INT 15 B RDY 16 B 17 STROBE B0 18 B1 19 VSS 20 40 VDD 39 RD/WE 38 WR/RE 37 TPB 36 A RDY 35 A STROBE 34 A0 33 A1 32 A2 31 A3 30 A4 29 A5 28 A6 27 A7 26 B7 25 B6 24 B5 23 B4 22 B3 21 B2
CDP1851 Programming Modes
(8) PORT A DATA PINS Accept Input Data Output Data Transfer Input/Output Data (2) PORT A HANDSHAKING PINS READY, STROBE (8) PORT B DATA PINS Accept Input Data (2) PORT B HANDSHAKING PINS READY, STROBE
MODE Input
Output Bidirectional (Port A Only)
READY, STROBE Input Handshaking for Port A
Output Data Must be Previously Set to Bit-Programmable Mode Programmed Individually as Inputs or Outputs
READY, STROBE Output Handshaking for Port A
Bit-Programmable
Programmed Individually as Inputs or Outputs
Programmed Individually as Inputs or Outputs
Programmed Individually as Inputs or Outputs
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1056.2
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CDP1851, CDP1851C
Absolute Maximum Ratings
DC Supply-Voltage Range, (VDD) (Voltage Referenced to VSS Terminal) CDP1851 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to+11V CDP1851C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA Device Dissipation Per Output Transistor For TA = Full Package-Temperature Range (All Package Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mW Operating-Temperature Range (TA) Package Type D, H . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 36 12 Maximum Storage Temperature Range (TSTG) . . . . -65oC to +150oC Maximum Lead Temperature (During Soldering) At Distance 1/16 1/32 inch (1.59 0.79mm) from Case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
At TA = Full Package-Temperature Range. For Maximum Reliability, Operating Conditions Should be Selected so that Operation is Always within the Following Ranges: LIMITS CDP1851 CDP1851C MAX 10.5 VDD MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER DC Operating Voltage Range Input Voltage Range
MIN 4 VSS
Functional Diagram
DATA BUS DATA BUS BUFFER SECTION A A0 A1 A2 A3 A4 A5 A6 A7 READY STROBE
CLOCK CS RA0 RA1 WR/RD RD/WR TPB CLEAR
ADDRESS DECODE AND READ/ WRITE LOGIC
MODE CONTROL AND STATUS REGISTERS
A INT B INT
INTERRUPT MASKING AND LOGIC
SECTION B
B0 B1 B2 B3 B4 B5 B6 B7 READY STROBE
FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1851 AND CDP1851C
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CDP1851, CDP1851C
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, Unless Otherwise Specified CONDITIONS CDP1851 PARAMETER Quiescent Device Current IDD VO (V) Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low-Level (Note 2) Output Voltage High Level (Note 2) Input Low Voltage IOL 0.4 0.5 IOH 4.6 9.5 VOL VOH VIL 0.5, 4.5 0.5, 9.5 Input High Voltage VlH 0.5, 4.5 0.5, 9.5 Input Leakage Current IlN Any Input 0, 5 0, 10 IDD1 Input Capacitance Output Capacitance NOTES: 1. Typical values are for TA = 25oC and nominal VDD. 2. IOL = IOH = 1A 3. Operating current is measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with open output (worst-case frequencies for CDP1802A system operating at maximum speed of 3.2MHz). CIN COUT VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 MIN 1.6 2.6 -1.15 -2.6 4.9 9.9 3.5 7 (NOTE1) TYP 0.01 1 3.2 5.2 -2.3 -5.2 0 0 5 10 1.5 6 5 10 MAX 50 200 0.1 0.1 1.5 3 1 2 1 1 3 12 7.5 15 MIN 1.6 -1.15 4.9 3.5 LIMITS CDP1851C (NOTE1) TYP 0.02 3.2 -2.3 0 5 1.5 5 10 MAX 200 0.1 1.5 1 1 3 7.5 15 UNITS A A mA mA mA mA V V V V V V V V A A A A mA mA pF pF
Three-State Output Leakage Current Operating Current (Note 3)
IOUT
Functional Description
The CDP1851 has four modes of operation: input, output, bidirectional, and bit-programmable. Port A is programmable in all modes; port B is programmable in all but the bidirectional mode. A control byte must be loaded into the control register to program the ports. In the input and output modes, each port has two handshaking signals, STROBE and RDY. In the bidirectional mode, port A has four handshaking signals: A RDY and A STROBE for input, B RDY and B STROBE for output. If port A is programmed in the bidirectional mode, port B must be programmed in the bit-programmable mode. Each terminal of port A or B may be individually programmed for input or output in the bitprogrammable mode. Since handshaking is not used in this mode, the RDY and STROBE lines may also be used for bitprogramming if port A is not in the bidirectional mode. Input Mode When a peripheral device has data to input, it sends a STROBE pulse to the PlO. The leading edge of this pulse clears the RDY line, inhibiting further transmission from the peripheral. The trailing edge of the STROBE pulse latches the data into the PlO buffer register and also activates the INT line to signal the CPU to read this data. The lNT pin can be wired to the INT pin of the CPU or the EF lines for polling. The CPU
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CDP1851, CDP1851C
then executes an input or a load instruction, depending on the mapping technique used. In either case the proper code must be asserted on the RAO, RA1, and CS lines to read the buffer register (see Table 6). The INT line is deactivated on the leading edge of TPB. The trailing edge of TPB sets the RDY line to signal the peripheral that the port is ready to be loaded with new data. If RDY is low when the input mode is entered (i.e. after a reset), a "dummy" read must be done to set RDY high and signal the peripheral device that the port is ready to be loaded. Output Mode A peripheral STROBE pulse sent to the PlO generates an interrupt to signal the CPU that the peripheral device is ready for data. The CPU executes the proper output or store instruction. Data are then read from memory and placed on the bus. The data are latched into the port buffer at the end of the window when RE/WE = 0 and WR/RE = 1. The RDY line is also set at this time, indicating to the peripheral that there is data in the port buffer. The INT line is deactivated at the beginning of the window. After the peripheral reads valid port data, it can send another STROBE pulse, clearing the RDY line and activating the INT line as in the input mode. Bidirectional Mode This mode programs port A to function as both an input and output port. The bidirectional feature allows the peripheral to
TPB MRD MWR TPA A0 A1 A2 CDP1800 A3 FAMILY A4 P A5 A6 A7 VDD 10k INT BUS 0-7 B INT A INT BUS 0-7 TPB WR/RE RD/WE CLOCK RA0 RA1 PIO NO. 1 CDP1851 A RDY B RDY A STROBE B STROBE PORT A0 - A7 PORT B0 - B7
control port direction by using both sets of handshake signals. The port A handshaking pins are used to control input data from peripheral to PlO, while the port B handshaking pins are used to control output data from PlO to peripheral. Data are transferred in the same manner as the input and output modes. Since A INT is used for both input and output, the status register must be read to determine what condition caused A INT to be activated (see Table 5). Bit-Programmable Mode This mode allows individual bits of port A or port B to be programmed as inputs or outputs. To output data to bits programmed as outputs, the CPU loads a data byte into the 8-bit port as in the output mode (no handshaking). Only bits programmed for outputs latch this data. Data must be stable when reading from bits programmed as inputs, since the input bits do not latch. When the CDP1851 inputs data to the CPU the CPU also reads the output bits latched during the last output cycle. The RDY and STROBE lines may be used for I/O by using the STROBE/RDY I/O control byte in Table 2. An additional feature available in the bit-programmable mode is the ability to generate interrupts based on input/output byte combinations. These interrupts can be programmed to occur on logic conditions (AND, OR, NAND, and NOR) generated by the eight I/O lines of each port (The STROBE and RDY lines cannot generate interrupts).
CS
ADDRESS REGISTER ADDRESS 8001 8002 8003 8004 8008 800C SELECTS No. 1 Control/Status Reg No. 1 Port A No. 1 Port B No. 2 Control/Status Reg No. 2 Port A No. 2 Port B
TPB WR/RE RD/WE CLOCK RA0 RA1 CS A INT B INT PIO NO. 2 CDP1851 A RDY B RDY A STROBE B STROBE PORT A0 - A7 PORT B0 - B7
FIGURE 2. MEMORY SPACE I/O. THIS CONFIGURATION ALLOWS UP TO FOUR CDP1851s TO OCCUPY MEMORY SPACE 8XXX WITH NO ADDITIONAL HARDWARE (A4-A5 AND A6-A7 ARE USED AS RA0 AND RA1 ON THE THIRD AND FOURTH PIO's)
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CDP1851, CDP1851C Programming
Initialization and Controls The CDP1851 PlO must be cleared by a low on the CLEAR input during power-on to set it for programming. Once programmed, modes can be changed without clearing except when exiting the bit-programmable mode. A low on the CLEAR input sets both ports to the input modes, disables interrupts, unmasks all bit-programmed interrupt bits, and resets the status register, A RDY, and B RDY. Mode Setting The control register must be sequentially loaded with the appropriate mode set control bytes in order as shown in Table 1 (i.e. input mode then output mode, etc.). Port A is set with the SET A bit = 1 and port B is set with the SET B bit = 1. If a port is set to the bit-programmable mode, the bit-programming control byte from Table 2 must be loaded. A bit is programmed for output with the I/O bit = 1 and for input with the I/O bit = 0. The STROBE and RDY lines may be programmed for input or output with the STROBE/RDY control byte of Table 2. Input data on the STROBE and RDY lines is detected by reading the status register. When using the STROBE or RDY lines for output, the control byte must be loaded every time output data is to be changed. To program logical conditions that will generate an interrupt, the interrupt control byte of Table 3 must be loaded. An interrupt mask of the eight I/O lines may be loaded next, if bit D4 (mask follows) of the interrupt control byte = 1. The I/O lines are masked if the corresponding bit of the interrupt mask register is 1, otherwise it is monitored. Any combination of masked bits are permissible, except all bits masked (mask = FF). INT Enable Disable To enable or disable the INT line in all modes, the interrupt ENABLE/DISABLE byte must be loaded (see Table 4). Interrupts can also be detected by reading the status register (see Table 5). All interrupts should be disabled when programming or false interrupts may occur. The INT outputs are open drain NMOS devices that allow wired O Ring (use 10K pull-up registers).
GENERATE CLEAR PULSE AT PIN 13
SET PORTS A AND B TO INPUT, OUTPUT, OR BIT-PROGRAMMABLE MODE USING TABLE 1
YES
IS EITHER PORT SET TO THE BIT-PROGRAMMABLE MODE 3
NO
PERFORM FOLLOWING SEQUENCE BEFORE PROGRAMMING PORT A TO BIDIRECTIONAL MODE NOW SET PORT A TO BIDIRECTIONAL MODE, IF DESIRED SET BIT DIRECTION USING TABLE 2 SET MASTER INTERRUPT ENABLE/DISABLE USING TABLE 4 WILL INTERRUPTS BE USED FOR BIT-PROGRAMMED PORT? NO MAIN PROGRAM
REPEAT FOR EACH BIT-PROGRAMMABLE PORT
YES REPEAT FOR EACH BIT-PROGRAMMABLE PORT SET BIT LOGICAL CONDITIONS AND MASKING USING TABLE 3
FIGURE 3. A FLOW CHART GUIDE TO CDP1851 MODE PROGRAMMING NOTES: 1. STROBE/READY I/O Control Byte (Table 2) is also used to output data to STROBE and READY lines when bit-programmed. 2. Status register (Table 2) is used to input data from STROBE and READY lines when bit-programmed. 3. Interrupt status is also read from status register.
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CDP1851, CDP1851C
TABLE 1. (RA1 = 0, RA0 = 1) (NOTE 1) MODE SET Input Output Bit-Programmable Bidirectional NOTE: 1. Modes should be set in order as shown in Table 1. If either port is set for bit-programmable mode, the two following control bytes should immediately follow: TABLE 2. (RA1 = 0, RA0 = 1) 7 Bit-Programming (Note 1) STROBE/RDY I/O Control (Notes 2 - 8) NOTES: 1. Output = 1, Input = 0 2. (D1) 0 = Port A, 1 = Port B 3. (D2) 0 = No change to RDY line function, 1 = Change per bit (D6) 4. (D3) 0 = No change to STROBE line function, 1 = Change per bit (D7) 5. (D4) RDY line output data 6. (D5) STROBE line output data 7. (D6) RDY line used as: Output = 1 Input = 0 8. (D7) STROBE line used as: Output = 1 Input = 0 If interrupts will be used for either bit-programmed port, the following control bytes should be loaded. TABLE 3. (RA1 = 0, RA0 = 1) INTERRUPT CONTROL Logical Conditions and Mask NOTES: 1. (D3) 0 = Port A, 1 = Port B 2. (D4) 0 = No change in mask, 1 = Mask follows (See Table 3A) 3. (D5)(D6) 0, 0 = NAND; 1, 0 = OR; 0, 1 = NOR; 1, 1 = AND TABLE 3A. (RA1 = 0, RA0 = 1) INTERRUPT CONTROL Mask Register (If D4 = 1) NOTE: 1. If Bn Mask = 1 then mask Bit (for n = 0 to 7) 7 B7 Mask 6 B6 Mask 5 B5 Mask 4 B4 Mask 3 B3 Mask 2 B2 Mask 1 B1 Mask 0 B0 Mask 7 0 6 D6 5 D5 4 D4 3 D3 2 1 1 0 0 1 I/O7 D7 6 I/O6 D6 5 I/O5 D5 4 I/O4 D4 3 I/O3 D3 2 I/O2 D2 1 I/O1 D1 0 I/O0 D0
7 0 0 1 1
6 0 1 1 0
5 X X X X
4 Set B Set B Set B X
3 Set A Set A Set A Set A
2 X X X X
1 1 1 1 1
0 1 1 1 1
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CDP1851, CDP1851C
TABLE 4. (RA1 = 0, RA0 = 1) INTERRUPT CONTROL Interrupt Enable/Disable NOTES: 1. INT Enable = 1, INT Enabled = 0, INT Disabled 2. A/B = 0, Port A = 1, Port B TABLE 5. (RA1 = 0, RA0 = 1) 7 Status Register NOTES: 1. All Modes (D0) B INT status (1 means set) (D1) A INT status (1 means set) 2. Bidirectional Mode Only (D2) 1 = A INT was caused by A STROBE (D3) 1 = A INT was caused by B STROBE 3. Bit-Programmable Mode (D4) A RDY input data (D5) A STROBE input data (D6) B RDY input data (D7) B STROBE input data TABLE 6. CPU CONTROLS (NOTE 1) CS 0 X X X X 1 1 1 1 1 1 NOTE: 1. Read = RD/WE = 1 and WR/RE = 0 is latched on trailing edge of CLOCK. TABLE 7. MEMORY I/O USE RD/WE INPUT I/O Space Memory Space MRD MWR WR/RE INPUT TPB MRD TPB INPUT TPB TPB D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 7 INT Enable 6 X 5 X 4 X 3 A/B 2 0 1 0 0 1
RA1 X 0 X X X 0 0 1 1 1 1
RA0 X 0 X X X 1 1 0 0 1 1
RD/WE X X 0 1 1 1 0 1 0 1 0
WR/RE X X 0 1 1 0 1 0 1 0 1
ACTION No-op bus three-stated No-op bus three-stated No-op bus three-stated No-op bus three-stated No-op bus three-stated Read status register (Note 1) Load control register Read port A (Note 1) Load port A Read port B (Note 1) Load port B
} }
PIO Terminal
CPU Terminals
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CDP1851, CDP1851C Function Pin Definition
CLOCK (Input): Positive input pulse that latches READ and CS on its trailing edge. CS - CHIP SELECT (Input) A high-level voltage at this input selects the CDP1851 PlO. RA0 - REGISTER ADDRESS 0 (Input): This input and RA1 are used to select either the ports or the control/status registers. RA1 - REGISTER ADDRESS 1(Input): See RAO BUS 0 - BUS 7: Bidirectional CPU data bus. CLEAR (Input) A low-level voltage at this input resets both ports to the input mode, and also resets the status register, A RDY, B RDY, and interrupt enable (disabling interrupts). A INT - A INTERRUPT (Output): A low-level voltage at this output indicates the presence of one of the interrupt conditions listed in Table 3. This output is an open-drain NMOS device (to allow wired O Ring) and must be tied to a pullup resistor, normally 10k. B INT - B INTERRUPT (Output): A low-level voltage at this output indicates the presence of one of the interrupt conditions listed in Table 3. This output is also an open-drain NMOS device and must be tied to a pullup resistor. B RDY - B READY (Output): This output is a handshaking or data bit I/O line in the bitprogrammable mode. TPB (Input): A positive input pulse used as a data load, set, or reset strobe. WR/RE - WRITE/READ ENABLE (Input): A positive input used to write data from the CDP1851 to the CPU bus. RD/WE - READ/WRITE ENABLE (Input): A positive input used to read data from the CPU bus to the CDP1851 bus. VDD: Positive supply voltage. A STROBE (Input): An input handshaking line for port A in the input, output, and bidirectional modes. It can also be used as a data bit I/O line when port A is in the bit-programmable mode. ARDY - AREADY (Output): A output handshaking line or data bit I/O line. A0 - A7: Data input or output lines for port A. B STROBE (Input): An input handshaking line for port B in the input and output modes, and for port A when it is in the bidirectional mode. It can be used as a data bit I/O line in the bit-programmable mode except when port A is not programmed as bidirectional. B0 - B7: Data input or output lines for port B. VSS Ground
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CDP1851, CDP1851C
N0 N1 N2 TPA MRD TPB CDP1802 VDD 10k INT BUS 0-7 RA0 RA1 CS CLOCK RD/WE WR/RE TPB B INT A INT BUS 0-7 CDP1851 PORT B0 - B7 A RDY B RDY A STROBE B STROBE PORT A0 - A7
RA0 BUS 0-7 RA1 CS CLOCK RD/WE WR/RE TPB CDP1851 A INT B INT
A RDY B RDY A STROBE B STROBE PORT A0 - A7
PORT B0 - B7
FIGURE 4. I/O SPACE I/O
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CDP1851, CDP1851C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, tr, tf = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF LIMITS CDP1851 PARAMETER INPUT MODE SEE FIGURES 4 AND 5 Minimum Setup Times: Chip Select to CLOCK tCSCL 5 10 RD/WE to CLOCK tRWCL 5 10 WR/RE to CLOCK tWRCL 5 10 Data in to STROBE tDlST 5 10 Minimum Hold Times: Chip Select After CLOCK tHCSCL 5 10 Address After TPB tHATPB 5 10 Data In After STROBE tHSTDl 5 10 Data Bus Out After Address tHADOH 5 10 Propagation Delay Times: TPB to INT tPINT 5 10 STROBE to INT tSTlNT 5 10 TPB to RDY tTPRDY 5 10 STROBE to RDY tSTRDY 5 10 Minimum Pulse Widths: CLOCK tWCL 5 10 TPB tWTPB 5 10 STROBE tWST 5 10 Access Time, Address to Data Bus Out tADA 5 10 NOTES: 1. Typical values are for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. 50 25 50 25 75 40 75 40 75 40 75 40 -50 -25 50 25 325 165 200 100 200 100 250 125 260 130 75 40 75 40 100 50 325 165 75 40 120 60 120 60 120 60 120 60 0 0 75 40 500 250 300 150 300 150 375 200 400 200 120 60 120 60 150 75 500 250 50 50 75 75 75 75 -50 50 325 200 200 250 260 75 75 100 325 75 120 120 120 120 0 75 500 300 300 375 400 120 120 150 500 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD (V) MIN (NOTE 1) TYP (NOTE 2) MAX MIN CDP1851C (NOTE 1) TYP (NOTE 2) MAX UNITS
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CDP1851, CDP1851C Test Circuit and Waveforms
VDD
1k A INT 50pF 1k B INT 50pF CDP1851 B A, B tPINT tWINT 10% tSTINT A INPUT SIGNAL 50% 50%
50%
FIGURE 5. INTERRUPT SIGNAL PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS
RDY tSTRDY INT tWST STROBE tDIST DATA-IN tWTPB tHSTDI tSTINT tPINT tTPRDY
TPB tWCL CLOCK = (TPA) tCSCL CS tWRCL WR/RE = (MRD) MEMORY SPACE RD/WE = (MWR) RD/WE = (MRD) tRWCL tHCSCL
I/O SPACE WR/RE = (TPB) tHATPB RA1/RA0 VALID PORT ADDRESS IO OR II tADA DATA BUS tHADOH
FIGURE 6. INPUT MODE TIMING WAVEFORMS
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CDP1851, CDP1851C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF LIMITS CDP1851 VDD (V) (NOTE 1) TYP (NOTE 2) MAX CDP1851C (NOTE 1) TYP (NOTE 2) MAX
PARAMETERS OUTPUT MODE SEE FIGURES 4 AND 6 Minimum Setup Times: Chip Select to CLOCK tCSCL
MIN
MIN
UNITS
5 10
-
50 25 75 40 75 40 50 25 80 40
75 40 120 60 120 60 75 40 120 60
-
50 75 75 50 80 -
75 120 120 75 120 -
ns ns ns ns ns ns ns ns ns ns
RD/WE to CLOCK
tRWCL
5 10
WR/RE to CLOCK
tWRCL
5 10
Address to WRITE (Note 3)
tAW
5 10
Data Bus to WRITE (Note 3)
tDW
5 10
Minimum Hold Times: Chip Select After CLOCK tHCSCL 5 10 Address After WRITE (Note 3) tHAW 5 10 Data Bus After WRITE (Note 3) tHDW 5 10 Propagation Delay Times: WRITE to Data Out (Note 3) tWDO 5 10 WRITE to INT (Note 3) tWINT 5 10 WRITE to RDY (Note 3) tWRDY 5 10 STROBE to lNT tSTlNT 5 10 STROBE to RDY tSTRDY 5 10 225 125 300 150 350 175 200 100 260 130 350 200 450 225 525 275 300 150 400 200 225 300 350 200 260 350 450 525 300 400 ns ns ns ns ns ns ns ns ns ns 75 40 50 25 50 25 120 60 75 40 75 40 75 50 50 120 75 75 ns ns ns ns ns ns
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CDP1851, CDP1851C
Dynamic Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF LIMITS CDP1851 VDD (V) (NOTE 1) TYP (NOTE 2) MAX CDP1851C (NOTE 1) TYP (NOTE 2) MAX
PARAMETERS Minimum Pulse Widths: CLOCK tWCL
MIN
MIN
UNITS
5 10
-
75 40 100 50 175 90
120 60 150 75 275 150
-
75 100 175 -
120 150 275 -
ns ns ns ns ns ns
STROBE
tWST
5 10
WRITE (Note 3)
tWW
5 10
NOTES: 1. Typical values are for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. 3. WRITE is the overlap of RD/WE = 0 and WR/RE = 1.
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CDP1851, CDP1851C
INT tWINT RDY tWRDY STROBE tWCL tWTPB tWST tSTRDY tSTINT
CLOCK = (TPA) tHCSCL CS tCSCL
DATA-OUT tWRCL WR/RE = (MRD) MEMORY SPACE RD/WE = (MWR) tWDO
VALID DATA OUT
tWW (NOTE 1) WR/WE = (TPB) I/O SPACE t RWCL RD/WE = (MRD) tAW RA1/RA0 tHAW
VALID PORT ADDRESS IO OR II tDW tDW
DATA BUS
VALID DATA
NOTE: 1. Write is the overlap of WR/RE = 1 and RD/WE = 0 FIGURE 7. OUTPUT MODE TIMING WAVEFORMS
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